#ifndef __UDF_GLOBAL_SYS_H
#define __UDF_GLOBAL_SYS_H

#include <stdint.h>
#include "sdk_ifs_udk_cfg.h"
#include "develop_def.h"
//#include "GPIO_Driver.h"
//#include "udp_def.h"


// frame define
typedef enum{
	eFRAME_TIMING_8BIT = 0,
	eFRAME_TIMING_PSEUDO_FLOATING = 1,
	eFRAME_FFT1D_PSEUDO_FLOATING = 2,
	eFRAME_FFT2D_PSEUDO_FLOATING = 3,
	eFRAME_POINTRST_ABS = 4,
}eFRAME_class_t;

typedef enum{
	eDRAW_SMALL_FRAME = 0,  // chirp帧
	eDRAW_CHIRP_SUM = 1,    // chirp和
	eDRAW_FRAME = 2,        // chirps
	eDRAW_FFT1D = 3,        // fft1d
	eDRAW_FFT1D_MEAN = 4,   // fft1d 均值
	eDRAW_FFT1D_MINUS = 5,  // fft1d 减均值
	eDRAW_FFT2D = 6,        // fft2d
	eDRAW_CFAR_VEL = 7,     // cfar 速度向
	eDRAW_CFAR_RANGE = 8,   // cfar 距离向
	eDRAW_CFAR_RV = 9,      // cfar 距离向
	eDRAW_POINTRST = 10,    // fft1d 点云结果
	eDRAW_DBSCAN  = 11,     // fft1d DBSCAN结果
	eDRAW_FFT1D_FRAME_DIFF = 12, // fft1d 帧间相减
	eDRAW_ZDPPLR = 13, // 零多普勒
	eDRAW_ZDPPLR_DIFF = 14,// 零多普勒帧间差
}eDraw_name_t;

typedef enum{
	eDRAW_ANTALL = 0,           // 所有天线
	eDRAW_ANT1 = 1,             // 天线1
	eDRAW_ANT2 = 2,             // 天线2
	eDRAW_ANT1_CALIB = 3,       // 天线1校正
	eDRAW_ANT2_CALIB = 4,       // 天线2校正
	eDRAW_ANT1_ADD_ANT2 = 5,    // 天线1+天线2
	eDRAW_ANT1_MINUS_ANT2 = 6,  // 天线1-天线2
}eDraw_name_id_t;

struct frame_info {
	uint8_t version;
	uint8_t interval_10_100_ms;
	uint16_t data_len;

	uint8_t pack_total;
	uint8_t pack_curr;	
	eFRAME_class_t frame_class;
	uint8_t samp_ant;
	
	uint16_t samp_num;
	uint16_t samp_chirp;
	
	uint8_t draw_id;
	eDraw_name_t draw_name;
	eDraw_name_id_t draw_name_id;
	uint8_t draw_opt;
};

typedef void (*FUNC_DATA_SEND_t)(uint8_t*,int);

struct frame_struct{
	uint8_t* pDataSrc;
	uint16_t DataSrc_ChirpInc;
	FUNC_DATA_SEND_t send_frame;
	FUNC_DATA_SEND_t send_data;
	struct frame_info frame_info;
	uint8_t Proto_MVersion;
};

#define FRAME_INFO_VERSION (0x20)

#define GET_ADDRESS(offset) (offset|(BBE_ABUF_BASE&0xF0000000))
#define GET_OFFSET(addr) (addr&0x0FFFFFFF)

#if 1
#define UDF_DBSCAN_NOISE          ( -1 )
#define UDF_DBSCAN_IDLE           ( 0 )
#define CLUSTER_MAX_NUM           ( 10 )
//dbscan input points struct
typedef struct {
		int16_t x;
		uint16_t y;
		int32_t r;
		uint8_t vIdx;
		uint8_t visited;
		uint8_t corePt;
		int8_t  clusterID;
		uint32_t abs;
} DBSCANPT;

typedef struct {
		uint32_t ptNum;
		DBSCANPT pt[FRAME_MAX_NUM];
} DBSCANFRAME;
		
typedef struct
{
		uint8_t ptNum;
		uint8_t idx[FRAME_MAX_NUM];
} DBSCANNB;

struct dbscan{
		DBSCANFRAME  dbscanFrame;
		DBSCANNB     nbA;
		DBSCANNB     nbB;
};
#else
/* db scan */

#define UDF_CLUSTER_MAX_NUM       ( 20 )
#define UDF_DBSCAN_NOISE          ( -1 )
#define UDF_DBSCAN_IDLE           ( 0 )

#define CLUSTER_MAX_NUM           ( 20 )
#define CLUSTERBUF_NUM            ( 10 )

typedef struct {
		uint8_t epsRIdx;
		uint8_t epsVIdx;
		uint8_t epsSinPhiIdx;
		uint8_t minPts;
} DBSCANCFG;
//dbscan input points struct
typedef struct {
		int16_t rIdx;
		int8_t vIdx;
		int8_t sinPhiIdx;
		uint8_t visited;
		uint8_t corePt;
		int8_t  clusterID;
	uint32_t abs;
} DBSCANPT;
typedef struct {
		uint8_t ptNum;
		DBSCANPT pt[FRAME_MAX_NUM];
} DBSCANFRAME;

typedef struct {
		int16_t rIdx;
		int8_t vIdx;
		int8_t sinPhiIdx;
} CLUSTERPT;
typedef struct {
		uint32_t numClu;
		CLUSTERPT cluBuf[CLUSTER_MAX_NUM];
} CLUSTERPTS;
typedef struct {
		uint32_t loopIdx;
		CLUSTERPTS clu[CLUSTERBUF_NUM];
} CLUSTERBUF;
		
//dbscan output result struct
typedef struct {
		int32_t rIdxMean;
		int32_t vIdxMean;
		int32_t sinPhiIdxMean;
		uint32_t abs;
} clusterRpt;
typedef struct {
		uint8_t numCluster;
		clusterRpt cluster[UDF_CLUSTER_MAX_NUM];
} DBSCANOUT;
//dbscan temp result struct
typedef struct
{
		uint8_t ptNum;
		uint8_t idx[FRAME_MAX_NUM];
} DBSCANNB;

struct dbscan{
	DBSCANFRAME  dbscanFrame;
	DBSCANOUT    dbscanClu;
	DBSCANNB     nbA;
	DBSCANNB     nbB;
	DBSCANCFG    cfg;
	uint16_t * divFac;
};

struct dbscan2{
	DBSCANFRAME  dbscanFrame;
	DBSCANOUT    dbscanClu;
	DBSCANNB     nbA;
	DBSCANNB     nbB;
	DBSCANCFG    cfg;
	CLUSTERBUF   clusterBuf;
	uint16_t * divFac;
};

struct dbscan_sp{
	DBSCANOUT    dbscanClu;
	DBSCANCFG    cfg;
	uint16_t *   divFac;
	uint8_t      rsv[FRAME_MAX_NUM*(1+1+2)];
};
#endif
/* 预定义 */
#if 1
#define ANA1_CFG0_DEFAULT (0x00000000|0xC0) // datasheet: default:0x000000C0
#define ANA1_CFG1_DEFAULT (0x18300000) // datasheet: default:0x18300040
#define ANA1_CFG2_DEFAULT (0x58108A00) // datasheet: default:0xF380AB00
	
#define ANA2_CFG0_DEFAULT (0x000000C0|0xC0) // datasheet: default:0x000000C0
#define ANA2_CFG1_DEFAULT (0x10000040) // datasheet: default:0x18300040
#define ANA2_CFG2_DEFAULT (0xF080AB00) // datasheet: default:0xF380AB00
	
#define ANA3_CFG0_DEFAULT (0x000000C0) // datasheet: default:0x000000C0
#define ANA3_CFG1_DEFAULT (0x18300000) // datasheet: default:0x18300040
#define ANA3_CFG2_DEFAULT (0x58108A00) // datasheet: default:0xF380AB00

#define ANA4_CFG0_DEFAULT (0x00000000|0xC0) // datasheet: default:0x000000C0
#define ANA4_CFG1_DEFAULT (0x18300000) // datasheet: default:0x18300040
#define ANA4_CFG2_DEFAULT (0x58108A00) // datasheet: default:0xF380AB00


#define UDP_CFG_RAMP_WAVE0_WAVE1_ONCE ( 0x00003101 )
#define UDP_CFG_RAMP_WAVE0_WAVE1_INF  ( 0x00003100 )
#define UDP_CFG_RAMP_WAVE0_INF        ( 0x00003000 )
#define UDP_CFG_RAMP_WAVE0_WAVE1_32_TIMES ( 0x00003120)

#define UDP_CFG_RAMP_PLL_23G      ( 0x00FC0000 )
#define UDP_CFG_RAMP_PLL_23G2     ( 0x01100000 )
#define UDP_CFG_RAMP_PLL_24G01    ( 0x01610000 )
#define UDP_CFG_RAMP_PLL_24G      ( 0x01600000 )

#define XTAL20M_RAMP_0G_1US       ( 0x00000008 )
#define XTAL20M_RAMP_0G_10US      ( 0x00000064 )
#define XTAL20M_RAMP_0G1_10US     ( 0x03330064 )
#define XTAL20M_RAMP_0G1_496US    ( 0x00101360 )
#define XTAL20M_RAMP_0G1_10US_M   ( 0x80000000 | XTAL20M_RAMP_0G1_10US )

#define XTAL20M_RAMP_0G25_34US    ( 0x025A0154 ) // 0.25G 34us
#define XTAL20M_RAMP_0G25_30US    ( 0x02AA012C ) // 0.25G 30us
#define XTAL20M_RAMP_0G25_30US_M  ( 0x80000000 | XTAL20M_RAMP_0G25_30US )    // -0.25G 30us

#define XTAL20M_RAMP_0G8_110US    ( 0x0253044C ) // 0.8G 110us
#define XTAL20M_RAMP_0G8_30US     ( 0x0888012C ) // 0.8G 30us
#define XTAL20M_RAMP_0G8_60US     ( 0x04440258 ) // 0.8G 60us
#define XTAL20M_RAMP_0G8_30US_M   ( 0x80000000 | XTAL20M_RAMP_0G8_30US )     // -0.25G 30us

/* 40Mhz */

#define XTAL40M_RAMP_0G_1US       ( 0x00000014 )
#define XTAL40M_RAMP_0G_5US       ( 0x00000064 )
#define XTAL40M_RAMP_0G_10US      ( 0x000000C8 )
#define XTAL40M_RAMP_0G1_200US    ( 0x00140FA0 )
#define XTAL40M_RAMP_0G_440US     ( 0x00002260 )
#define XTAL40M_RAMP_0G_100US     ( 0x000007D0 )
//#define XTAL40M_RAMP_0G_40US      ( 0x00000320 )

#define XTAL40M_RAMP_0G1_540US    ( 0x00072A30 )
#define XTAL40M_RAMP_0G1_470US    ( 0x000824B8 )
//#define XTAL40M_RAMP_0G1_490US    ( 0x00082648 )
#define XTAL40M_RAMP_0G1_496US    ( 0x000826C0 )
#define XTAL40M_RAMP_0G1_100US    ( 0x002807D0 )
#define XTAL40M_RAMP_0G1_10US     ( 0x019900C8 )
#define XTAL40M_RAMP_0G1_20US     ( 0x00CC0190 )
#define XTAL40M_RAMP_0G1_40US     ( 0x00660320 )
#define XTAL40M_RAMP_0G1_10US_M   ( 0x80000000 | XTAL40M_RAMP_0G1_10US )

#define XTAL40M_RAMP_0G21_28US    ( 0x01330230 )
#define XTAL40M_RAMP_0G21_30US    ( 0x011E0258 )
#define XTAL40M_RAMP_0G21_30US_M  ( 0x80000000 | XTAL40M_RAMP_0G21_30US )

#define XTAL40M_RAMP_0G22_110US   ( 0x00510898 )	
#define XTAL40M_RAMP_0G22_30US    ( 0x012C0258 )
#define XTAL40M_RAMP_0G22_40US    ( 0x00E10320 )
#define XTAL40M_RAMP_0G22_40US_M  ( 0x80000000 | XTAL40M_RAMP_0G22_40US )
#define XTAL40M_RAMP_0G22_30US_M  ( 0x80000000 | XTAL40M_RAMP_0G22_30US )
#define XTAL40M_RAMP_0G22_55US    ( 0x00A3044C )

#define XTAL40M_RAMP_0G22_830US   ( 0x000A40D8 ) // 0.22G 830us
#define XTAL40M_RAMP_0G22_860US   ( 0x000A4330 ) // 0.22G 860us
#define XTAL40M_RAMP_0G22_960US   ( 0x00094B00 ) // 0.22G 960us
#define XTAL40M_RAMP_0G22_440US   ( 0x00142260 ) // 0.22G 440us
#define XTAL40M_RAMP_0G22_220US   ( 0x00281130 ) // 0.22G 220us

#define XTAL40M_RAMP_0G22_17US    ( 0x02120154 ) // 0.22G 17us
#define XTAL40M_RAMP_0G22_28US    ( 0x01410230 ) // 0.22G 28us
#define XTAL40M_RAMP_0G22_15US    ( 0x0258012C ) // 0.22G 15us
#define XTAL40M_RAMP_0G22_15US_M  ( 0x80000000 | XTAL40M_RAMP_0G22_15US )   // -0.22G 15us

#define XTAL40M_RAMP_0G25_55US     ( 0x00BA044C ) // 0.25G  55us
#define XTAL40M_RAMP_0G25_60US     ( 0x00AA04B0 ) // 0.25G  60us
#define XTAL40M_RAMP_0G25_110US    ( 0x005D0898 ) // 0.25G  110us
#define XTAL40M_RAMP_0G25_2000US   ( 0x00059C40 ) // 0.25G 2000us
#define XTAL40M_RAMP_0G25_2000US_M ( 0x80000000 | XTAL40M_RAMP_0G25_2000US ) // -0.25G 2000us
#define XTAL40M_RAMP_0G25_475US    ( 0x0015251C ) // 0.25G 475us
#define XTAL40M_RAMP_0G25_475US_M  ( 0x80000000 | XTAL40M_RAMP_0G25_475US )  // -0.25G 475us

#define XTAL40M_RAMP_0G25_34US    ( 0x012D02A8 ) // 0.25G 34us
#define XTAL40M_RAMP_0G25_30US    ( 0x01550258 ) // 0.25G 30us
#define XTAL40M_RAMP_0G25_30US_M  ( 0x80000000 | XTAL40M_RAMP_0G25_30US )    // -0.25G 30us

#define XTAL40M_RAMP_0G8_110US    ( 0x01290898 ) //  0.8G 110us
#define XTAL40M_RAMP_0G8_55US     ( 0x0253044C ) //  0.8G 55us
#define XTAL40M_RAMP_0G8_60US     ( 0x022204B0 ) //  0.8G 60us
#define XTAL40M_RAMP_0G8_30US     ( 0x04440258 ) //  0.8G 30us
#define XTAL40M_RAMP_0G8_30US_M   ( 0x80000000 | XTAL40M_RAMP_0G8_30US )    // -0.8G 30us
#define XTAL40M_RAMP_0G8_5US      ( 0x19990064 ) //  0.8G 5us
#define XTAL40M_RAMP_0G8_5US_M    ( 0x80000000 | XTAL40M_RAMP_0G8_5US )


#if APPLICATION_MODE == APPLICATION_MODE_ROM_START
#define RAMP_GET(x) XTAL40M_##x
#elif APPLICATION_MODE == APPLICATION_MODE_XIP_START
#define RAMP_GET(x) XTAL20M_##x
//#define RAMP_GET(x) XTAL40M_##x
#else
#error xxxx
#endif


#if 1 /*ANA默认配置*/

/*cfg0 define*/
#define ANA1_XTAL_CAP (8)
#define ANA1_XTAL_DIS (0)
#define ANA1_VDD_DIS  (0)
#define ANA1_LRC_TUNE (1)
#define ANA1_PLL1_EN  (0)
#define ANA1_PLL2_EN  (0)
#define ANA1_ADC_EN   (0)
#define ANA1_ADC_CH1_EN   (0)
#define ANA1_ADC_CH0_EN   (0)
#define ANA1_LDO_IF_EN    (0)
#define ANA1_LDO_RF_EN    (0)

#define ANA1_PLL3_EN (0ul)
#define ANA1_HPF1 (2) /*0-100k 1-140k 2-200k 3-260k*/
#define ANA1_HPF2 (2) /*0-50k 1-100k 2/3-160k*/
#define ANA1_ANT2_RX_EN (0)
#define ANA1_ANT1_RX_EN (0)
#define ANA1_PGA1 (0) /*0~3*/
#define ANA1_PGA2 (0) /*0~3*/
#define ANA1_PGA3 (0) /*0~3*/

/*cfg2 define*/
#define ANA1_PA1_POWER (3)
#define ANA1_PA2_POWER (3)
#define ANA1_VDD12_DIS (0)

/*cfg0 define*/
#define ANA2_XTAL_CAP (8)
#define ANA2_XTAL_DIS (0)
#define ANA2_VDD_DIS  (0)
#define ANA2_LRC_TUNE (1)
#define ANA2_PLL1_EN  (1)
#define ANA2_PLL2_EN  (1)
#define ANA2_ADC_EN   (1)
#define ANA2_ADC_CH1_EN   (1)
#define ANA2_ADC_CH0_EN   (1)
#define ANA2_LDO_IF_EN    (1)
#define ANA2_LDO_RF_EN    (1)
/*cfg1 define*/
#define ANA2_PLL3_EN (1ul)
#define ANA2_HPF1 (3) /*0-100k 1-140k 2-200k 3-260k*/
#define ANA2_HPF2 (3) /*0-50k 1-100k 2/3-160k*/
#define ANA2_ANT2_RX_EN (1)
#define ANA2_ANT1_RX_EN (1)
#define ANA2_PGA1 (2) /*0~3*/
#define ANA2_PGA2 (2) /*0~3*/
#define ANA2_PGA3 (2) /*0~3*/
/*cfg2 define*/
#define ANA2_PA1_POWER (3)
#define ANA2_PA2_POWER (3)
#define ANA2_VDD12_DIS (0)

/*cfg0 define*/
#define ANA3_XTAL_CAP (8)
#define ANA3_XTAL_DIS (0)
#define ANA3_VDD_DIS  (0)
#define ANA3_LRC_TUNE (1)
#define ANA3_PLL1_EN  (1)
#define ANA3_PLL2_EN  (1)
#define ANA3_ADC_EN   (1)
#define ANA3_ADC_CH1_EN   (1)
#define ANA3_ADC_CH0_EN   (1)
#define ANA3_LDO_IF_EN    (0)
#define ANA3_LDO_RF_EN    (0)

#define ANA3_PLL3_EN (1ul)
#define ANA3_HPF1 (3) /*0-100k 1-140k 2-200k 3-260k*/
#define ANA3_HPF2 (3) /*0-50k 1-100k 2/3-160k*/
#define ANA3_ANT2_RX_EN (0)
#define ANA3_ANT1_RX_EN (0)
#define ANA3_PGA1 (2) /*0~3*/
#define ANA3_PGA2 (0) /*0~3*/
#define ANA3_PGA3 (0) /*0~3*/

/*cfg2 define*/
#define ANA3_PA1_POWER (3)
#define ANA3_PA2_POWER (3)
#define ANA3_VDD12_DIS (0)


/*cfg0 define*/
#define ANA4_XTAL_CAP (8)
#define ANA4_XTAL_DIS (1)
#define ANA4_VDD_DIS  (1)
#define ANA4_LRC_TUNE (1)
#define ANA4_PLL1_EN  (0)
#define ANA4_PLL2_EN  (0)
#define ANA4_ADC_EN   (0)
#define ANA4_ADC_CH1_EN   (0)
#define ANA4_ADC_CH0_EN   (0)
#define ANA4_LDO_IF_EN    (0)
#define ANA4_LDO_RF_EN    (0)

#define ANA4_PLL3_EN (0ul)
#define ANA4_HPF1 (2) /*0-100k 1-140k 2-200k 3-260k*/
#define ANA4_HPF2 (2) /*0-50k 1-100k 2/3-160k*/
#define ANA4_ANT2_RX_EN (0)
#define ANA4_ANT1_RX_EN (0)
#define ANA4_PGA1 (0) /*0~3*/
#define ANA4_PGA2 (0) /*0~3*/
#define ANA4_PGA3 (0) /*0~3*/

/*cfg2 define*/
#define ANA4_PA1_POWER (3)
#define ANA4_PA2_POWER (3)
#define ANA4_VDD12_DIS (1)

#endif


#define UDPCFG_ANA1_CFG0          ( ANA1_CFG0_DEFAULT | 0xC0 | (ANA1_XTAL_CAP<<20)|(ANA1_XTAL_DIS<<17)|(ANA1_VDD_DIS<<16)| (ANA1_LRC_TUNE<<14)|(ANA1_PLL1_EN<<13)|(ANA1_PLL2_EN<<12)|(ANA1_ADC_EN<<8)|(ANA1_ADC_CH1_EN<<3)|(ANA1_ADC_CH0_EN<<2)|(ANA1_LDO_IF_EN<<1)|ANA1_LDO_RF_EN)
#define UDPCFG_ANA1_CFG1          ( ANA1_CFG1_DEFAULT | (ANA1_PLL3_EN<<31)|(ANA1_HPF1<<14) | (ANA1_HPF2<<12) | (ANA1_ANT2_RX_EN<<9)|(ANA1_ANT1_RX_EN<<8)|(ANA1_PGA1<<4) | (ANA1_PGA2<<2) | ANA1_PGA3)
#define UDPCFG_ANA1_CFG2          ( ANA1_CFG2_DEFAULT | (ANA1_PA1_POWER<<26) | (ANA1_PA2_POWER<<19) | ANA1_VDD12_DIS)
																	  
#define UDPCFG_ANA2_CFG0          ( ANA2_CFG0_DEFAULT | 0xC0 | (ANA2_XTAL_CAP<<20)|(ANA2_XTAL_DIS<<17)|(ANA2_VDD_DIS<<16)| (ANA2_LRC_TUNE<<14)|(ANA2_PLL1_EN<<13)|(ANA2_PLL2_EN<<12)|(ANA2_ADC_EN<<8)|(ANA2_ADC_CH1_EN<<3)|(ANA2_ADC_CH0_EN<<2)|(ANA2_LDO_IF_EN<<1)|ANA2_LDO_RF_EN)
#define UDPCFG_ANA2_CFG1          ( ANA2_CFG1_DEFAULT | (ANA2_PLL3_EN<<31)|(ANA2_HPF1<<14) | (ANA2_HPF2<<12) | (ANA2_ANT2_RX_EN<<9)|(ANA2_ANT1_RX_EN<<8)|(ANA2_PGA1<<4) | (ANA2_PGA2<<2) | ANA2_PGA3)
#define UDPCFG_ANA2_CFG2          ( ANA2_CFG2_DEFAULT | (ANA2_PA1_POWER<<26) | (ANA2_PA2_POWER<<19) | ANA2_VDD12_DIS)

#define UDPCFG_ANA3_CFG0          ( ANA3_CFG0_DEFAULT | 0xC0 | (ANA3_XTAL_CAP<<20)|(ANA3_XTAL_DIS<<17)|(ANA3_VDD_DIS<<16)| (ANA3_LRC_TUNE<<14)|(ANA3_PLL1_EN<<13)|(ANA3_PLL2_EN<<12)|(ANA3_ADC_EN<<8)|(ANA3_ADC_CH1_EN<<3)|(ANA3_ADC_CH0_EN<<2)|(ANA3_LDO_IF_EN<<1)|ANA3_LDO_RF_EN)
#define UDPCFG_ANA3_CFG1          ( ANA3_CFG1_DEFAULT | (ANA3_PLL3_EN<<31)|(ANA3_HPF1<<14) | (ANA3_HPF2<<12) | (ANA3_ANT2_RX_EN<<9)|(ANA3_ANT1_RX_EN<<8)|(ANA3_PGA1<<4) | (ANA3_PGA2<<2) | ANA3_PGA3)
#define UDPCFG_ANA3_CFG2          ( ANA3_CFG2_DEFAULT | (ANA3_PA1_POWER<<26) | (ANA3_PA2_POWER<<19) | ANA3_VDD12_DIS)
																	  
#define UDPCFG_ANA4_CFG0          ( ANA4_CFG0_DEFAULT | 0xC0 | (ANA4_XTAL_CAP<<20)|(ANA4_XTAL_DIS<<17)|(ANA4_VDD_DIS<<16)| (ANA4_LRC_TUNE<<14)|(ANA4_PLL1_EN<<13)|(ANA4_PLL2_EN<<12)|(ANA4_ADC_EN<<8)|(ANA4_ADC_CH1_EN<<3)|(ANA4_ADC_CH0_EN<<2)|(ANA4_LDO_IF_EN<<1)|ANA4_LDO_RF_EN)
#define UDPCFG_ANA4_CFG1          ( ANA4_CFG1_DEFAULT | (ANA4_PLL3_EN<<31)|(ANA4_HPF1<<14) | (ANA4_HPF2<<12) | (ANA4_ANT2_RX_EN<<9)|(ANA4_ANT1_RX_EN<<8)|(ANA4_PGA1<<4) | (ANA4_PGA2<<2) | ANA4_PGA3)
#define UDPCFG_ANA4_CFG2          ( ANA4_CFG2_DEFAULT | (ANA4_PA1_POWER<<26) | (ANA4_PA2_POWER<<19) | ANA4_VDD12_DIS)
																	  
#define UDPCFG_DP_CFG0            ( (UDFDEF_ANT_NUM - 1)<< 28 |(UDFDEF_RAMP_CNT - 1) << 20 | UDFDEF_ADCSAMP_NUMLOG      << 16 |	UDFDEF_ADCSAMP_OFFSET      << 8 |	 0 << 2 | 0 << 0)
#define UDPCFG_DP_CFG1            ( 0 << 8 | UDFDEF_CIC_SEC  << 4 | UDFDEF_DOWN_SEC << 0)
#define UDPCFG_DP_CFG2            ( (GET_OFFSET(UDFDEF_ADDR_ADCSAMP)/0x4000) << 24 |0 << 20 |0 << 16)
#endif


#if 1 /* 结构体定义 Idx默认为扩大4096倍*/
#define STRUCT_DEF \
struct{ \
uint32_t  pow;\
uint32_t  rIdx;\
int32_t   vIdx;\
int32_t   sinPhiIdx;\
uint32_t  presence_flag;\
uint8_t   info1;\
uint8_t   info2;\
}

#define MAX_EPC_NUM       (32)

typedef STRUCT_DEF epc_unit_t;
struct epc_target{
	STRUCT_DEF;
	uint16_t unprocess_flag;
};
struct epc
{
	uint16_t frame_interval;
	uint16_t target_cnt;

	uint16_t range_res_mm;
	int16_t  vel_res_mm_s;

	uint16_t rangeMax;
	uint8_t  chirpMax;
	uint8_t  angleMax;

	struct epc_target target[MAX_EPC_NUM];
};
#endif

#endif
